1. Field of the Invention
The present invention relates to a semiconductor device and a package structure thereof, and more particularly, a semiconductor device integrated with a converter and a package structure thereof.
2. Description of the Prior Art
Electronic devices usually include various components, and each component has its own operation voltage. Therefore, DC-DC voltage converters are required in electronic devices to change the voltage level (step up or step down) and maintain the required voltage supply stable. Due to different demands for power source, the DC-DC converters develop into many different types originally from the Buck/Step Down converter and the Boost/Step Up converter.
The conventional Buck converter is composed of a high-side NMOSFET device and a low-side NMOSFET device. The high-side NMOSFET device and the low-side NMOSFET device are usually disposed in the same package structure for being electrically connected to the circuit board.
Please refer to FIG. 1. FIG. 1 illustrates a schematic diagram of a package structure of a conventional Buck converter. As shown in FIG. 1, the package structure 10 of the conventional Buck converter includes a lead frame 12, a high-side NMOSFET device 14, a low-side NMOSFET device 16, a Schottky diode 18 and a sealant 20. The lead frame 12 includes a first lead 12a, a second lead 12b, a third lead 12c, a fourth lead 12d, a fifth lead 12e, a sixth lead 12f, a seventh lead 12g, an eighth lead 12h, a first chip holder 12i and a second chip holder 12j. The first lead 12a and the second lead 12b are connected to the first chip holder 12i, while the fifth lead 12e, the sixth lead 12f, and the seventh lead 12g are connected to the second chip holder 12j. The high-side NMOSFET device 14 is disposed on the first chip holder 12i, in which a drain of the high-side NMOSFET device 14 is electrically connected to the first chip holder 12i, and a source 14b and a gate 14c of the high-side NMOSFET device 14 are respectively electrically connected to the seventh lead 12g and the eighth lead 12h by means of metal wires 22. Furthermore, the low-side NMOSFET device 16 and the Schottky diode 18 are disposed on the second chip holder 12j. The drain of the low-side NMOSFET device 16 and an N-terminal of the Schottky diode 18 are electrically connected to the second chip holder 12j, and the source 16b of the low-side NMOSFET device 16 is electrically connected to a P-terminal of the Schottky diode 18 and the fourth lead 12d by means of metal wires 22. The gate 16c of the low-side NMOSFET device 16 is electrically connected to the third lead 12c by means of metal wires 22. Accordingly, the first lead 12a and the second lead 12b stand for the drain of the high-side NMOSFET device 14, and the third lead 12c stands for the gate 16c of the low-side NMOSFET device 16. The fourth lead 12d stands for the source 16b of the low-side NMOSFET device 16, and the fifth lead 12e, the sixth lead 12f, and the seventh lead 12g stand for the source 14b of the high-side NMOSFET device 14 and the drain of the low-side NMOSFET device 16. The eighth lead 12h stands for the gate 14c of the high-side NMOSFET device 14.
In the package structure 10 of the conventional Buck converter, the drain of the high-side NMOSFET device 14 and the drain of the low-side NMOSFET device 16 are both at a lower side of the chip. To prevent electrical connection between the drain of the high-side NMOSFET device 14 and the drain of the low-side NMOSFET device 16, the lead frame 12 provides the first chip holder 12i and the second chip holder 12j which are electrically insulated from each other to separately dispose the high-side NMOSFET device 14 and the low-side NMOSFET device 16. Accordingly, a gap that is generally 250 micrometer (μm) is required between the first chip holder 12i and the second chip holder 12j. Furthermore, to prevent the high-side NMOSFET device 14 and the low-side NMOSFET device 16 from being disposed outside the first chip holder 12i and the second chip holder 12j respectively, a width between a side of the high-side NMOSFET device 14 and an edge of the first chip holder 12i and a width between a side of the low-side NMOSFET device 16 and an edge of the second chip holder 12j should be also 250 μm.
Consequently, the gap between the high-side NMOSFET device 14 and the low-side NMOSFET device 16 requires at least 750 μm. With the fixed size of the package structure 10, the dimensions of the high-side NMOSFET device 14 and the low-side NMOSFET device 16 are confined. Therefore, turn-on resistances between the drain and the source 14b of the high-side NMOSFET device 14 and between the drain and the source 16b of the low-side NMOSFET device 16 are increased due to the decrease of device chip, and the power loss during voltage conversion increases correspondingly.
In addition, in the package structure 10 of the conventional Buck converter, in order to electrically connect the source 14b of the high-side NMOSFET device 14 to the drain of the low-side NMOSFET device 16, the source 14b of the high-side NMOSFET device 14 is electrically connected to the seventh lead 12g by means of metal wires 22, and the seventh lead 12g is connected to the second chip holder 12j. Therefore, the resistance between the source 14b of the high-side NMOSFET device 14 and the drain of the low-side NMOSFET device 16 is restricted by the transmission path and the resistance may further cause the power loss during voltage conversion.
Accordingly, to decrease the power loss due to the package structure of the conventional Buck converter is really the subject to be improved in this field.